`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    13:15:53 04/29/2011 
// Design Name: 
// Module Name:    VGAcontrol 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
 module scoredisplay (F, vgadisp,hcounter, vcounter,blank);

	
	input [3:0] F;
	output reg vgadisp;
	input blank;
	input [10:0] hcounter, vcounter;
always@(*)	begin

case(F)
4'd1: begin 
	vgadisp= ~blank &&
	(vcounter>= 83 && vcounter<92 && hcounter>=426 && hcounter< 456) || (vcounter>= 47 && vcounter<83 && hcounter>=438 && hcounter< 444) || (vcounter>= 47 && vcounter<56 
	&& hcounter>=432 && hcounter< 438)||(vcounter>= 56 && vcounter<65 && hcounter>=426 && hcounter< 432);
end
4'd2: begin
vgadisp=~blank &&
(vcounter>= 47 && vcounter<56 && hcounter>=432 && hcounter< 456) ||(vcounter>= 65 && vcounter<74 && hcounter>=432 && hcounter< 456)
			||(vcounter>= 83 && vcounter<92 && hcounter>=432 && hcounter< 456)
			||(vcounter>= 56 && vcounter<65 && hcounter>=450 && hcounter< 456)
		||(vcounter>= 74 && vcounter<83 && hcounter>=432 && hcounter< 438);
end
4'd3: begin
vgadisp=~blank &&
(vcounter>= 47 && vcounter<56 && hcounter>=432 && hcounter< 456) ||
			(vcounter>= 65 && vcounter<74 && hcounter>=432 && hcounter< 456) ||
			(vcounter>= 83 && vcounter<92 && hcounter>=432 && hcounter< 456) ||
			(vcounter>= 56 && vcounter<65 && hcounter>=450 && hcounter< 456) ||
			(vcounter>= 74 && vcounter<83 && hcounter>=450 && hcounter< 456) ;
			end   


4'd4: begin
vgadisp=~blank &&
(vcounter>= 47 && vcounter<74 && hcounter>=432 && hcounter< 438) ||
(vcounter>= 47 && vcounter<92 && hcounter>=450 && hcounter< 456) ||
			(vcounter>= 65 && vcounter<74 && hcounter>=438 && hcounter< 450);
			end   






4'd5: begin
vgadisp=~blank &&
(vcounter>= 47 && vcounter<56 && hcounter>=432 && hcounter< 456) 
			||(vcounter>= 65 && vcounter<74 && hcounter>=432 && hcounter< 456) ||
			(vcounter>= 83 && vcounter<92 && hcounter>=432 && hcounter< 456) ||
			(vcounter>= 56 && vcounter<65 && hcounter>=432 && hcounter< 438) ||
			(vcounter>= 74 && vcounter<83 && hcounter>=450 && hcounter< 456);
			end   




4'd6: begin
vgadisp=~blank &&
(vcounter>= 47 && vcounter<56 && hcounter>=432 && hcounter< 456) ||
(vcounter>= 65 && vcounter<74 && hcounter>=432 && hcounter< 456) ||
(vcounter>= 83 && vcounter<92 && hcounter>=432 && hcounter< 456) ||
(vcounter>= 56 && vcounter<65 && hcounter>=432 && hcounter< 438) ||
(vcounter>= 74 && vcounter<83 && hcounter>=450 && hcounter< 456) ||
(vcounter>= 74 && vcounter<83 && hcounter>=432 && hcounter< 438) ;
			end   






4'd7: begin
vgadisp=~blank &&
(vcounter>= 47 && vcounter<56  && hcounter>=432 && hcounter< 456) ||
(vcounter>= 47 && vcounter<92 && hcounter>=450 && hcounter< 456) ;
			
end


4'd8: begin
vgadisp=~blank &&
(vcounter>= 47 && vcounter<56 && hcounter>=432 && hcounter< 456) ||
(vcounter>= 65 && vcounter<74 && hcounter>=432 && hcounter< 456) ||
(vcounter>= 83 && vcounter<92 && hcounter>=432 && hcounter< 456) ||
(vcounter>= 56 && vcounter<65 && hcounter>=450 && hcounter< 456) ||
(vcounter>= 74 && vcounter<83 && hcounter>=450 && hcounter< 456) ||
(vcounter>= 47 && vcounter<92 && hcounter>=432 && hcounter< 438) ;
end


4'd9: begin
vgadisp=~blank &&
(vcounter>= 47 && vcounter<56 && hcounter>=432 && hcounter< 456) ||
(vcounter>= 65 && vcounter<74 && hcounter>=432 && hcounter< 456) ||
(vcounter>= 83 && vcounter<92 && hcounter>=432 && hcounter< 456) ||
(vcounter>= 56 && vcounter<65 && hcounter>=432 && hcounter< 438) ||
(vcounter>= 56 && vcounter<65 && hcounter>=450 && hcounter< 456) ||
(vcounter>= 74 && vcounter<83 && hcounter>=450 && hcounter< 456);
			end   



4'h0: begin
vgadisp=~blank &&
(vcounter>= 47 && vcounter<56 && hcounter>=432 && hcounter< 456) ||
(vcounter>= 83 && vcounter<92 && hcounter>=432 && hcounter< 456) ||
(vcounter>= 47 && vcounter<92 && hcounter>=432 && hcounter< 438) ||
(vcounter>= 47 && vcounter<92 && hcounter>=450 && hcounter< 456);
end
default: begin
end
endcase

end
endmodule